1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device, and more particularly, to a manufacturing method for a semiconductor device in order to acquire a HEMT (High electron mobility transistor) or a MESFET (Metal-Semiconductor Field Effect Transistor), for example.
2. Description of the Related Art
Hitherto, a semiconductor device has been proposed which has a structure having a through hole called recess in a contact layer and having a gate electrode therein (as in Japanese Patent Application Laid-Open (JP-A) No. 2007-157918, for example).
On the other hand, one semiconductor device may have a double recess structure having a small through hole called inner recess within a through hole called wide recess, and having a gate electrode imbedded in the small through hole and also disposed on the edge part thereof (refer to “Low Voltage Operation Power Heterojunction FET with Low on-resistance for Personal Digital Cellular Phones”, TECHNICAL REPORT OF IEICE (The Institute of Electronics, Information and Communication Engineers) ED98-215, MW98-178, ICD98-282 (1999-01), for example). The semiconductor device has an etching stopper layer for performing selective etching. For example, generally in a conventional InGaAs/AlGaAs (GaAs) semiconductor device, in order to use an organic acid-oxygenated water mixed solution or a BCl3/SF6 mixed gas to perform selective etching between two GaAs layers or two AlGaAs layers, an AlGaAs layer having a higher mixing ratio of Al (approximately 20% or higher) or an AlAs layer is used as an etching stopper layer.
However, because the AlGaAs layer with the higher mixing ratio of Al or AlAs layer as an etching stopper layer has a larger band gap than that of a GaAs layer or an InGaAs layer, conduction band discontinuity increases. The conduction band discontinuity becomes a barrier against electrons, which increases the contact resistance, for example, and results in a device with a larger parasitic resistance.
By the way, as a technology for reducing the contact resistance, methods for lowering the barrier at an interface between layers have been proposed (refer to JP-A Nos. 8-162647, 11-54837 and 2007-157918 for example). However, from the viewpoint of the implementation of etching with high precision, the methods are still not enough, and improvements thereon are being demanded today.